evaluation board for g = 1, 2, 5, 10; 10 mhz, 20 v/s programmable gain in-amp ad8250-evalz rev. 0 evaluation boards are only intended for device evaluation and not for production purposes. evaluation boards are supplied as is and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. no license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. analog devices reserves the right to change devices or specifications at any time without notice. trademarks and registered trademarks are the property of their respective owners. evaluation boards are not authorized to be used in life support devices or systems. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features quick evaluation on-board gain control switches sma connectors for high speed gain testing general description the ad8250-evalz is designed to enable quick evaluation of the ad8250 programmable gain instrumentation amplifier (pgia). the evaluation board includes on-board gain setting switches to quickly demonstrate the ad8250s software gain programmability. in addition, an external logic generator can be connected to the ad8250-evalz sma ports to test the pgias gain control. 06701-001 a1 tp4 wr tp5 a0 tp3 vout tp1 w2 w3 dgnd r6 2k ? w1 hi hi r7 2k ? 4 5 1 10 u1 ad8250 6 2 7 9 3 8 sw1 sw2 ?v s c3 0.1f c5 c6 c7 c4 0.1f vref jp1 r2 in? tp2 r1 r3 r5 in+ out r4 c8 c1 10f + +v s ?v s c2 10f + dgnd jp3 c10 gnd2 g nd1 r8 0 ? + v s hi tp6 c9 0.1f tp7 1 u2 2 3 5 4 adr392 +v s ?v s figure 1. schematic
ad8250-evalz rev. 0 | page 2 of 4 evaluation board hardware quick start guide by default, the ad8250-evalz is configured for gain change using the on-board switches, sw1 and sw2, as shown in table 1 . table 1. gain setting using the on-board switches w3 (jumper) sw2 sw1 gain in place low low 1 in place low high 2 in place high low 5 in place high high 10 table 2. default settings (from the factory) name default status w1, w2, w3 in place (tied) jp1, jp3, r1, r2, r3, r5 shorted by design (on trace) using external logic to change gain the ad8250-evalz accepts external logic signals such as those from logic generators or fpgas. to change gains using external logic signals, jumpers w1, w2, and w3 must be removed. only then will the a0, a1, and wr pins on the ad8250 be directly tied to tp3, tp4, and tp5 (and to the respective sma connectors). external logic can be tied via the test points tp3, tp4 and tp5, or via the respective sma connector. termination the ad8250-evalz has 50 traces leading to the a0, a1, and wr pins. however, it does not have terminations to those pins. if terminations are added, remove jumper w1, jumper w2, and jumper w3. rfi filter an rfi filter pattern is included at the input traces of the ad8250-evalz. r1 and r2 are shorted. the shorted traces must be cut before r1 and r2 are placed on the board. output filter an output filter pattern is included at the output trace of the ad8250-evalz. to use r3 or r5 in a filter, cut the shorted traces prior to placing resistors in those locations. reference to level shift the output, a nonzero reference voltage can be applied to ref. by default, ref is tied to analog gnd. cutting the trace at jp1 opens the connection between ref and analog gnd. analog and digital ground analog and digital grounds are tied at jp3. to sever the connection between them, jp3 can be cut with a knife to open the connection between the two grounds. gain selection (from ad8250 data sheet) this section shows users how to configure the ad8250 for basic operation. logic low and logic high voltage limits are listed in the specifications section of the ad8250 data sheet. typically, logic low is 0 v and logic high is 5 v; both voltages are meas- ured with respect to dgnd. refer to the specifications table of the ad8250 for the permissible voltage range of dgnd. the gain of the ad8250 can be set using two methods. transparent gain mode the easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to a0 and a1. figure 2 shows an example of this gain setting method, referred to through- out the data sheet as transparent gain mode. tie wr to the negative supply to engage transparent gain mode. (on the ad8250-evalz board, put the w3 jumper in place.) in this mode, any change in voltage applied to a0 and a1 from logic low to logic high, or vice versa, immediately results in a gain change. tabl e 3 is the truth table for transparent gain mode and figure 2 shows the ad8250 configured in transparent gain mode. +15 v ?15v ?15v a0 a1 wr +in +5v +5v ?in 10 f0.1f 10 f0.1f g = 10 dgnd dgnd ref ad8250 06701-002 note: 1. in transparent gain mode, wr is tied to ? v s . the voltage levels on a0 and a1 determine the gain. in this example, both a0 and a1 are set to logic high, resulting in a gain of 10. figure 2. transparent gain mode, a0 and a1 = high, g = 10 table 3. truth table logic leve ls for transparent gain mode wr (w3) a1 (sw2) a0 (sw1) gain ?v s (in place) low low 1 ?v s (in place) low high 2 ?v s (in place) high low 5 ?v s (in place) high high 10
ad8250-evalz rev. 0 | page 3 of 4 latched gain mode some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same pcb. in such cases, devices can share a data bus. the gain of the ad8250 can be set using wr as a latch, allowing other devices to share a0 and a1. figure 3 shows a schematic using this method, known as latched gain mode. (on the ad8250-evalz, remove the w1, w2, and w3 jumpers, and drive a0, a1, and wr with external logic to test this gain setting mode.) the ad8250 is in this mode when wr is held at logic high or logic low, typically 5 v and 0 v, respectively. the voltages on a0 and a1 are read on the downward edge of the wr signal as it transitions from logic high to logic low. this latches in the logic levels on a0 and a1, resulting in a gain change. see the truth table listing in table 4 for more informa- tion on these gain changes. +15 v ?15v a0 a1 wr +in ?in 10 f0.1f 10 f0.1f dgnd dgnd ref ad8250 a0 a1 wr +5v +5v +5v 0v 0v 0v g = previous state g = 10 06701-003 + ? note: 1. on the downward edge of wr, as it transitions from logic high to logic low, the voltages on a0 and a1 are read and latched in, resulting in a gain change. in this example, the gain switches to g = 10. figure 3. latched gain mode, g = 10 table 4. truth table logic le vels for latched gain mode 1 1 1 1 gain high to low low low change to 1 high to low low high change to 2 high to low high low change to 5 high to low high high change to 10 low to low x 2 x 2 no change low to high x 2 x 2 no change high to high x 2 x 2 no change 1 jumper w1, jumper w2, and jumper w3 must be removed and external logic must be used to test latched gain mode. 2 x = dont care. on power-up, the ad8250 defaults to a gain of 1 when in latched gain mode. in contrast, if the ad8250 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on a0 and a1 upon power-up. timing for latched gain mode in latched gain mode, logic levels at a0 and a1 have to be held for a minimum setup time, t su , before the downward edge of wr latches in the gain. similarly, they must be held for a minimum hold time of t hd after the downward edge of wr to ensure that the gain is latched in correctly. after t hd , a0 and a1 may change logic levels but the gain does not change (until the next downward edge of wr ). the minimum duration that wr can be held high is t w r -high , and t w r -low is the minimum duration that wr can be held low. digital timing specifications are listed in the specification section of the ad8250 data sheet. the time required for a gain change is dominated by the settling time of the amplifier. a timing diagram is shown in figure 4 . when sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the ad8250. feedthrough can be minimized by decreasing the edge rate of the logic signals. furthermore, careful layout of the pcb also reduces coupling between the digital and analog portions of the board. a0, a1 wr t su t hd t wr-high t wr-low 0 6701-004 figure 4. timing diagram for latched gain mode
ad8250-evalz rev. 0 | page 4 of 4 ordering information ordering guide model package description ad8250-evalz 1 evaluation board 1 z = rohs compliant part. esd caution ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. eb06701-0-6/07(0)
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